Patent attributes
A method of identifying faulty programmable interconnect resources of a field programmable gate array (FPGA) may be carried out during manufacturing testing and/or during normal on-line operation. The FPGA resources are configured into a working area and a self-testing area. The working area maintains normal operation of the FPGA throughout on-line testing. Within the self-testing area, programmable interconnect resources of the FPGA are grouped and comparatively tested for faults. Upon the detection of one or more faults within a group of programmable interconnect resources, the group of resources is subdivided for further comparative testing in order to minimize a region of the group of resources including the fault for each fault. Once the region of the group of resources which includes the fault is minimized, the wires within the minimized region are comparatively tested in order to determine which wire includes the faulty resource or resources. Once the wire which includes the faulty resource is determined, a variety of testing configurations may be utilized to identify the faulty resource within the wire.
