US Patent 6978343 Error-correcting content addressable memory

A content addressable memory (CAM) device having an error correction function. The CAM device includes an array of CAM cells, row parity storage elements and column parity storage elements. The row parity storage elements store row parity values that correspond to contents of respective rows of the CAM cells, and the column parity storage elements store column parity values that correspond to respective columns of the CAM cells. A bit error in the array is detected through row and column parity checking that uniquely identifies the row and column location of the error and enables correction of the error.