Patent attributes
A level shifter includes first and second P-type TFTs for latching a level of first and second output nodes, first and second N-type TFTs for setting the level of the first and second output nodes, and a drive circuit. The drive circuit includes third to eighth N-type TFTs providing, in response to rising and falling edges of an input signal, a voltage higher than a threshold voltage of the first and second N-type TFTs, between the gate and source of the first and second N-type TFTs, and includes first and second capacitors and a resistor element. Accordingly, even if an amplitude voltage of an input signal is smaller than the threshold voltage of the first and second N-type TFTs, the level shifter operates normally.