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US Patent 6982487 Wafer level package and multi-package stack
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Patent
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Date Filed
September 22, 2003
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Date of Patent
January 3, 2006
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Patent Application Number
10665630
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Patent Citations Received
US Patent 12014958 Microfeature workpieces and methods for forming interconnects in microfeature workpieces
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US Patent 12132029 Integrating passive devices in package structures
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Patent Inventor Names
Hyeong-Seob Kim
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Tae-Gyeong Chung
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
6982487
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Patent Primary Examiner
Andy Huynh
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