Is a
Patent attributes
Patent Jurisdiction
Patent Number
Patent Inventor Names
Ely Tsern0
Richard E. Perego0
Stefanos Sidiropoulos0
Date of Patent
June 13, 2006
0Patent Application Number
106252760
Date Filed
July 23, 2003
0Patent Citations Received
Patent Primary Examiner
Patent abstract
A memory system architecture/interconnect topology that includes at least one point-to-point link between a master, and at least one memory subsystem. The memory subsystem includes a buffer device coupled to a plurality of memory devices. The memory system may be upgraded through dedicated point-to-point links and corresponding memory subsystems. The master communicates to the plurality of memory devices in each memory subsystem through the respective buffer device via each point-to-point link.
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