Patent attributes
A high power Doherty amplifier circuit having at least one input terminal and at least one output terminal comprising at least one carrier transistor (30) forming a main amplifier stage; at least one peak transistor (32) forming a peak amplifier stage; a first input line (27) connecting the input terminal (28) to an input (29) of the carrier transistor (30); a second input line (31) connecting the input terminal (28) to an input (63) of the peak transistor (32); a first output line (33) connecting the output terminal (56) to an output (49) of the carrier transistor (30); and a second output line (35) connecting the output terminal (56) to an output (75) of the peak transistor (32). A high power Doherty amplifier circuit package comprising a support structure (104) supporting circuit elements of the Doherty amplifier circuit; at least one input terminal (102) and at least one output terminal (96) both terminals being supported on the support structure (104); at least one carrier transistor (92) forming a main amplifier stage and at least one peak transistor (98) forming a peak amplifier stage both transistors being supported on the support structure (104); a first input network (106) connecting the input terminal (102) to an input of the carrier transistor (92); a second input network (100, 114, 116) connecting the input terminal (102) to an input of the peak transistor (98); a first output network (94, 108, 110) connecting the output terminal (96) to an output of the carrier transistor (92); and a second output network (112) connecting the output terminal (96) to an output of the peak transistor (98), and wherein the input and output networks are artificial transmission lines comprising serial circuits and/or parallel circuits of at least one capacitance and/or at least one inductance.
