Is a
Patent attributes
Current Assignee
Patent Jurisdiction
Patent Number
Patent Inventor Names
Jiin Lai0
Bi-Yun Yeh0
Sheng-Chung Wu0
Date of Patent
July 25, 2006
0Patent Application Number
101723320
Date Filed
June 14, 2002
0Patent Citations Received
Patent Primary Examiner
Patent abstract
The present invention provides a data memory controller that supports for the invert of data bus. Data transmitted from a memory is received in a chip set, which further transmits the data to a data processing apparatus. While receiving the memory data, the chip set doubles the bandwidth and reduces the frequency, such that the time margin for processing data is increased. In addition, after outputting data to the data processing apparatus, a first frame of data is compared to bus idle state to further reduce frequency of data invert and power consumption.
Timeline
No Timeline data yet.
Further Resources
No Further Resources data yet.