US Patent 7086017 Method of post-implementation simulation of a HDL design

A method of post-implementation simulation of a hardware description language (HDL) net list file, that does not match a HDL design file from which it was synthesized, comprises the steps of: creating a remap file which translates ports between the HDL net list file and the HDL design file; and simulating the HDL net list file utilizing the remap file and a (HDL) test bench file created for pre-implementation simulation of the HDL design file. The method may be executed in an integrated software environment or a batch software environment.