Patent attributes
A semiconductor memory device includes memory cell arrays; bit lines; word lines; a column selection line; and a sense amplifier comprising a first sense node connected to the first bit line, a second sense node connected to the second bit line, a first cross couple including two switching elements of first conduction type connected in series between the first sense node and the second sense node, and a second cross couple including two switching elements of second conduction type connected in series between the first sense node and the second sense node, a first node between the two switching elements in the first cross couple and a second node between the two switching elements in the second cross couple being connected to different power supplies via a plurality of routes, the sense amplifier selecting the routes on the basis of a potential on the column selection line.
