US Patent 7093223 Noise analysis for an integrated circuit model
Patent 7093223 was granted and assigned to Freescale Semiconductor on August, 2006 by the United States Patent and Trademark Office.
All edits
A method for designing and routing circuitry having reduced cross talk. Early noise analysis (22) is performed after global routing (12) but before detailed routing (28) in order to repair problems (24) before detailed routing (28) is performed. In one embodiment, the early noise analysis (22) is preceded by probabilistic extraction (16). In one embodiment, probabilistic extraction (16) includes determining a probability of occurrence for each configuration in a predetermined set of configurations (54). Probabilistic capacitance extraction is then performed (56). A probabilistic distributed coupled RC network is constructed using the extracted capacitances (60). In one embodiment, probabilistic extraction (16) includes estimating aggressor strength (20) using the probabilistic distributed coupled RC network.
US Patent 07093223 Noise analysis for an integrated circuit model US Patent 7093223 Noise analysis for an integrated circuit model
US Patent 07093223 Noise analysis for an integrated circuit model
Find more entities like US Patent 7093223 Noise analysis for an integrated circuit model
