US Patent 7095653 Common wordline flash array architecture

The memory area on a die required for row (X) and column (Y) decoders is reduced by a plurality of memory array blocks sharing wordlines to a single row decoder. During erase operations, the p-well of unselected memory array blocks is pulled negative to substantially the same potential as the wordline to avoid erase disturbances. During programming operations, the unselected p-wells are pulled high to avoid gate disturbances.