Patent attributes
Provided is a circuit for implementing the coding of a DVI (Digital Visual Interface) standard in a small size of hardware, at high speed, and with low power consumption. In a DVI coding circuit, the input of a number-of-levels comparison circuit 22 for judging which of the number of bits at a level “H” and the number of bits at a level “L” is larger in the input signal of the coding circuit is set at 7 bits. The output of a number-of-transitions decrease circuit 23 for decreasing the number of the transitions between adjacent two bits can be inverted for 4 bits on the basis of the output of the number-of-levels comparison circuit 22. A DC balance circuit 24 for keeping the direct current-wise balance of the output signal of the coding circuit includes a 4-bit register 31, a number-of-levels difference computation circuit 27, a condition decision circuit 28, a bit inversion circuit 29 and an addition circuit 30. The number-of-levels difference computation circuit 27 receives as its inputs the 8 bits of the output of the number-of-transitions decrease circuit 23 and the 4 bits of the input signal of the coding circuit.
