US Patent 7098717 Gate triggered ESD clamp

The clamp circuit of the present invention comprises a low voltage, thin oxide MOS transistor and a trigger element comprising a timing element and at least one inverter. The source and drain of the MOS transistor are connected between a first node and a second node. The timing element comprises a capacitive element and a resistive element connected between the first and second nodes. The inverter is connected between a third node between the capacitive element and the resistive element and the gate of the MOS transistor. Advantageously, one or both of the capacitive element and the resistive element is also implemented in low voltage, thin oxide MOS transistors.