US Patent 7100129 Hierarchical gcell method and mechanism

Patent 7100129 was granted and assigned to Cadence Design Systems on August, 2006 by the United States Patent and Trademark Office.

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Patent Inventor Names

Eric Nequist0

Jeffrey Scott Salowe0

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Patent abstract

A method of analyzing a design of an electronic circuit includes tessellating the design into a grid of rectangles, selecting at least one rectangle as a first level parent rectangle, and generating a plurality of second level child rectangles based on the first level parent rectangle.

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Official Website

https://pdfpiw.uspto.gov/.piw?Docid=07100129

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