US Patent 7101763 Low capacitance junction-isolation for bulk FinFET technology
All edits
The present invention provides a SiGe-based bulk integration scheme for generating FinFET devices on a bulk Si substrate in which a simple etch, mask, ion implant set of sequences have been added to accomplish good junction isolation while maintaining the low capacitance benefits of FinFETs. The method of the present invention includes providing a structure including a bottom Si layer and a patterned stack comprising a SiGe layer and a top Si layer on the bottom Si layer; forming a well region and isolation regions via implantation within the bottom Si layer; forming an undercut region beneath the top Si layer by etching back the SiGe layer; and filling the undercut with a dielectric to provide device isolation, wherein the dielectric has an outer vertical edge that is aligned to an outer vertical edge of the top Si layer.
US Patent 07101763 Low capacitance junction-isolation for bulk FinFET technology US Patent 7101763 Low capacitance junction-isolation for bulk FinFET technology
US Patent 07101763 Low capacitance junction-isolation for bulk FinFET technology
Find more entities like US Patent 7101763 Low capacitance junction-isolation for bulk FinFET technology
