US Patent 7103108 Digital signal processor transceiver

A digital signal processor transceiver uses a finite impulse response filter memory to construct a phase integrated angle at each clock cycle. The FIR filter memory is addressed by a multibit pattern and a time count which are used in conjunction to determine the address. Each data word of the FIR filter memory represents the sum of two tap points multiplied by their tap coefficients. Several of the most significant bits of the phase integrated angle are used to address look up tables for the signal's sine and cosine values. The address for the cosine look up table may further be phase compensated. Filter types other than a FIR filter may be used.