US Patent 7103624 Comparator circuit and method

A binary comparator circuit and a binary data comparison method for reducing a layout area and power consumption and/or increasing comparison speed. The binary data comparison circuit and method receive all N bits of each of a first binary data An−1An−2 . . . A1A0 and a second binary data Bn−1Bn−2 . . . B1B0, and compare the first binary data and the second binary data to determine which of the first binary data and the second binary data is larger according to the following equation:F(A≦B)=A(n−1)′·B(n−1)+(A(n−1)′+B(n−1))·{A(n−2)′·B(n−2)+(A(n−2)′+B(n−2)) . . . {A1′·B1+(A1′+B1)·(A0′+B0)}}where subscripts denote a position of a bit of the N-bit binary data and a prime (′) indicates that a bit is inverted, and outputting a signal corresponding to the comparison result.