Patent attributes
A multi-chip package is provided. A first die pad has a first chip attaching surface and a first unoccupied surface. A second die pad has a second chip attaching surface and a second unoccupied surface. The connecting structures are used for connecting the first die pad and the second die pad. The inner leads has wire connecting surfaces. The wire connecting surfaces, the first chip attaching surface and the second unoccupied surface face the same direction. A first chip has a first active surface and a first inactive surface. The first inactive surface is attached to the first chip attaching surface. A second chip has a second active surface and a second inactive surface. Part of the second active surface is attached to the second chip attaching surface. The wires are used for electrically connecting the first active surface and the second active surface to the wire connecting surfaces.
