US Patent 7106110 Clock dithering system and method during frequency scaling
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Patent Inventor Names
Cedric Lichtenau0
Erwin B. Cohen0
Jay G. Heaslip0
Mathew I. Ringler0
Miles G. Canada0
Thomas Pflueger0
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Patent abstract
A system and method of shifting a clock frequency of an integrated circuit device from a first frequency to a second frequency, including alternating between the first frequency and the second frequency according to a dithering pattern, the alternating occurring for a predetermined number of cycles; and setting the clock frequency to the second frequency after the predetermined number of cycles.
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US Patent 07106110 Clock dithering system and method during frequency scaling US Patent 7106110 Clock dithering system and method during frequency scaling
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Patent Number
071061100
Patent Number
71061100
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Patent Jurisdiction
Patent Number
071061100
Date of Patent
September 12, 2006
0Patent Application Number
107106810
Date Filed
July 28, 2004
0Official Website
Patent Primary Examiner
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US Patent 07106110 Clock dithering system and method during frequency scaling
Infobox
Is a
Patent jurisdiction
Patent number
07106110
Date of patent
September 12, 2006
Patent application number
10710681
Date Filed
July 28, 2004
Patent primary examiner
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