Patent attributes
A circuit arrangement includes a first phase locked loop to generate a first oscillator frequency, a second phase locked loop to generate a second oscillator frequency, a reference frequency emitter connected to a reference frequency input of both phase locked loops, and a signal attenuator and optionally a switch connected between a master signal output of the first (master) loop and an input of the second (slave) loop. In a method, a common reference frequency is provided to both loops, the first loop generates a first oscillator frequency, and the second loop generates a second oscillator frequency that matches the first oscillator frequency in at least one operating mode and optionally differs from the first oscillator frequency in another operating mode. The frequency matching in one of the modes involves feeding an attenuated signal from the first loop operating as a master into the second loop operating as a slave.
