US Patent 7116011 CPU surge reduction and protection

Methods and systems of providing power to a central processing unit (CPU) provide for enhanced surge protection and increased battery life. In one approach, an integrated circuit as a power output stage with an output node, and a voltage regulator coupled to the power output stage. The voltage regulator selectively switches the power output stage into a current ramp down mode based on detection of a voltage surge at the output node. The power output stage has an associated current ramp down rate. The CPU is coupled to the output node and a surge notification input of the power output stage, where the power output stage accelerates the current ramp down based on a notification signal from the CPU.