US Patent 7116605 Dual port SRAM cell

The present invention provides a SRAM that is capable of performing a writing and reading operations simultaneously without collision while reducing size of cell, by providing a dual port SRAM cell. For this, the dual port SRAM cell, including: a writing section having a first transistor for inputting a data input signal from a bit line in response to a control signal from a word line; a data storage section having three transistors for storing the data input signal from the outside through the writing section; and a reading section having two transistors for reading the data input signal stored in the data storage section in response to control signal from a common line.