Patent attributes
Techniques of designing a digital phase lock loop are disclosed. In one embodiment, the digital phase lock loop comprises a synchronization unit producing a producing a plurality of clock signals in accordance with a seed clock signal having a frequency, each of the clock signals having a modified frequency over the frequency of the seed clock signal and a phase shift from each other; a phase-frequency detection unit receiving an input signal and a feedback signal, and sampling the input signal and the feedback signal in accordance with the clock signals to determine differences in phase and frequency between the input signal and the feedback signal; a digital control oscillator receiving the clock signals and producing an output signal in reference to the differences from phase-frequency detection unit, and subsequently, a digitally controlled clock signal is produced.
