US Patent 7117236 Parallel adder-based DCT/IDCT design using cyclic convolution

The present invention provides a device and method for applying 1-D and 2-D DCT and IDCT transforms to sets of input data, typically 8×8 or 16×16 matricies of coefficients. In one embodiment, the present invention provides input lines, logic to pre-add input values and generate operands and one or more adder networks that effectively carry out the multiplication operations required to apply a DCT/IDCT transform. The device may apply a 1-D transform twice to accomplish a 2-D transform. Alternatively, the present invention may either include successive stages of logic for the second 1-D transform or it may send data transformed once back through the same logic to pre-add and adder networks for the second 1-D transform. Calculations may be carried out after Booth encoding of operands. The processing may be split between producing vp, a vector of sums of output values, and producing vn, a vector of differences of output values, which vectors may be recombined to produce an output vector v.