Patent attributes
A memory cell having a bit line contact and a method of manufacturing the memory cell is provided The memory cell may be a 6F2 or smaller memory cell. The bit line contact may have a contact hole bounded by insulating side walls, the contact hole may have a selective, epitaxially grown base layer, may be partially or completely filled with a doped polysilicon plug, and may have a silicide cap. The doped polysilicon plug may have an upper plug surface profile that is substantially free of concavities or substantially convex. Similarly, a storage node contact may comprise a doped polysilicon plug having an upper plug surface profile that is substantially free of concavities or that is substantially convex. Additionally, a semiconductor device having a conductive contact comprising a polysilicon plug may is provided. The plug may contact a capacitor structure.
