US Patent 7122414 Method to fabricate dual metal CMOS devices
All edits
Edits on 6 Sep, 2023
Golden AI
Edits made to:
Infobox (+1 properties)
Infobox
Patent Inventor Names
Hannu Huotari0
Edits on 31 Aug, 2023
Golden AI
Edits made to:
Article (+169 characters)
Article
Patent abstract
The present invention relates generally to barrier layers in transistor gate stacks in integrated circuits, and to processes for forming such gate stacks.
Edits on 22 Jul, 2023
Golden AI
Edits made to:
Infobox (-1 properties)
Infobox
Official Website
Edits on 22 May, 2023
Golden AI
Edits made to:
Infobox (+1/-1 properties)
US Patent 07122414 Method to fabricate dual metal CMOS devices US Patent 7122414 Method to fabricate dual metal CMOS devices
Infobox
Patent Number
07122414
Patent Number
7122414
Edits on 7 Jun, 2022
Golden AI
Edits made to:
Infobox (+1 properties)
Infobox
Website URL
Edits on 18 Nov, 2021
Golden AI
Edits made to:
Infobox (+7 properties)
US Patent 07122414 Method to fabricate dual metal CMOS devices
Infobox
Is a
Patent jurisdiction
Patent number
07122414
Date of patent
October 17, 2006
Patent application number
10601037
Date Filed
June 19, 2003
Patent primary examiner
Find more entities like US Patent 7122414 Method to fabricate dual metal CMOS devices
Use the Golden Query Tool to find similar entities by any field in the Knowledge Graph, including industry, location, and more.
