Patent attributes
A non-volatile semiconductor memory device with a small variation in capacitance-coupling to the stacked gate for memory miniaturization. The device has a memory cell array in which memory cells are arranged in array. Each cell has a first gate and a second gate on a semiconductor substrate. The first gate is formed, via a first gate insulating film, on each of device forming regions isolated by device-isolating insulating films. The second gate is formed on the first gate via a second gate insulating film. The first gate is patterned so that its portion is overlapped on the isolation insulating film from the device forming region. A protective insulating film is provided on the isolation film between the device forming regions and in the vicinity of the first gate. A charge-storage layer of each memory cell has at least two stacked conductive layers with a small isolation width at a low aspect ratio for burying isolation insulating films for high density, to easily fabricate in low cost. The side face of the lowest conductive layer meets the side portion of the isolation region. The highest conductive layer has the same width as or is wider than the lowest conductive layer. The first conductive layer is thin for decrease in aspect ratio for burying the insulating film. The second conductive layer has a specific thickness for attaining a desired capacitance between it and the control gate. The highest layer may be formed in self-alignment with the isolation region and stretched out by isotropic-etching.
