US Patent 7123096 Quadrature offset power amplifier

An amplifier having a first transistor with an output coupled to a common output node and a switch for coupling a control electrode of the first transistor to a first bias source to bias such first transistor to a conducting state during a relatively high power operating mode or for removing such control electrode from the first bias source to place the first transistor in a non-conducting condition during a relatively low power operating mode selectively in accordance with a control signal. A second transistor has an output coupled to the common output node and a second bias source coupled to a control electrode to the second transistor to bias such second transistor to a conducting state during both the relatively high power operating mode and the relatively low power operating mode. First circuitry is coupled between an output of the second transistor and the common output node providing a different impedance at the output of the second transistor during the relatively high power operating mode than during the relatively low power operating mode. Second circuitry is coupled between the common input node and the control electrode of the second transistor device. The insertion phases of the of the first circuitry and the second circuitry is such that one of the two provides a nominal ninety-degree (i.e., substantially (4n+1)π/2 radians, where n is an integer including zero) phase lead and the other of the two provides a nominal ninety-degree (i.e., substantially (4n+1)π/2 radians, where n is an integer including zero) phase lag.