Patent 7124230 was granted and assigned to Intel on October, 2006 by the United States Patent and Trademark Office.
A peripheral component interconnect-extended system that includes a bus bridge. The bus bridge includes an input queue adapted to receive a first request for data from a requesting device coupled to a first bus. The first bus is coupled to the bus bridge, and the first request containing a sequence identification information. The bus bridge also includes a data storage device to contain information to control the bus bridge, and a processor that associates a first unique identification code to the first request.