US Patent 7126400 Delay adjustment circuit, integrated circuit device, and delay adjustment method

A delay circuit includes a plurality of delay units DI to DN. An input signal IS is input to the delay circuit, and the delay circuit outputs a delay signal. A comparison circuit stores, to a comparison result register, comparison result data of a pulse width time of a pulse of a test input signal IS input to the delay circuit and delay times of delay signals DSM to DSN output from taps PM to PN of the delay circuit. An adjustment circuit adjusts the delay time of the delay signal in the delay circuit. Adjustment data ADT of the delay time is set based on the comparison result data read from the comparison result register. The delay time after adjustment is confirmed by again inputting the test input signal after the delay time has been adjusted, and again reading the comparison result data from the comparison result register.