Patent attributes
A new clock driver is described for the use in the phase detector of a clock and data recovery circuit (CDR). By building a resonant LC tank, whose center frequency is similar to the clock frequency, a low power clock driver is realized. A method based upon minimizing power consumption is described for determining the value of the programmable capacitance. A programmable capacitance adjusts the center frequency of the tank so it matches the frequency of the clock and a finite state machine at startup determines the value of this programmable capacitance. A criterion for tuning the center frequency of the tank is to choose the capacitance which leads to the lowest power consumption. A low Q tank affords a reasonable compromise between power efficiency and performance in the CDR circuit.
