Patent attributes
A power-down mode exit control circuit enables a memory device to exit from an initially set power-down mode state using a clock enable signal. Specifically, although a clock enable signal is inputted in an unstable state at an initial operation indicating that a supply of a supply voltage is started, the present invention provides the power-down mode exit control circuit which is capable of escaping from the power-down mode at an internally set correct time. For this, the present invention comprises: a clock enable signal sensor for sensing an activation or deactivation state of a clock enable signal; and a power-down mode exit signal generator for activating and outputting a power-down mode exit signal in accordance with the activation state of the clock enable signal sensed by the sensor, after storing information related to the deactivation state of the clock enable signal sensed by the sensor.
