Patent attributes
A method of optimizing clock network capacitance of an integrated circuit (IC) including identifying any crossover points between clock traces and signal traces and reducing clock trace to reference trace capacitance at identified crossover points. Each clock trace is shielded by ground traces routed on either side of the clock traces. The reducing of clock trace to reference trace capacitance may include narrowing the reference traces at identified crossover points. Narrowing of the reference traces at a crossover point reduces capacitance to compensate for additional capacitance between the clock trace and the signal trace. Narrowing may be performed by trimming or notching at the crossover points. Such capacitive compensation provides clock traces of the clock network with substantially uniform capacitance per unit length.
