US Patent 7132751 Memory cell using silicon carbide

A memory includes an insulating layer; a plurality of spaced-apart semiconductor lines formed on the insulating layer; and a plurality of spaced-apart conductive gate lines formed on the insulating layer. Each of the gate lines is disposed to intersect the plurality of semiconductor lines at a plurality of intersections. The semiconductor lines include a plurality of body regions disposed at the intersections, with each of the body regions including a channel formed from a silicon carbide material.