Patent attributes
A method and apparatus for measuring communications link quality provides accurate on-chip estimation of the difficulty of achieving a particular bit error rate (BER) for a communications link. A low cost/complexity accumulator circuit connected to internal signals from a clock/data recovery (CDR) circuit provides a measure of high frequency and low frequency jitter in a received signal. The low frequency jitter measurement is used to correct the high frequency jitter measurement which may otherwise contain error. The corrected output may be used to adjust operational characteristics of the link or otherwise evaluate the link for operating margin. The correction may be performed by subtracting a portion of the low frequency jitter measurement from the measured high frequency jitter, or the value of the low frequency jitter measurement may be used to select between two or more correction factors that are then applied to the high frequency jitter measurement.
