US Patent 7134108 Method for checking an IC layout

A method for checking an IC layout is used for checking the wire line width in the circuit layout. The IC includes at least a first metal layer having at least a wire, and the wire has a plurality of wire segments. The method includes the steps of checking the width of each wire segment, wherein if at least a narrow wire segment has a width smaller than a predetermined width, the narrow wire segment is removed; if there is at least a non-coupling wire segment not coupled to a voltage source in the remained wire segments, outputting the non-coupling wire and disposing a coupling wire to couple the non-coupling wire segment and the voltage source.