US Patent 7134112 Incremental routing in integrated circuit design
Patent 7134112 was granted and assigned to Xilinx on November, 2006 by the United States Patent and Trademark Office.
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Patent Inventor Names
Jason H. Anderson0
Sandor S. Kalman0
Vinay Verma0
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Patent abstract
A method for completing the routing of a partially routed design is provided. The unrouted pins are routed to generate a first plurality of nets that may contain shorts or overlaps between the nets. The nets are analyzed to obtain timing information, and then divided into a set of critical and a set of non-critical nets. The non-critical nets are hidden, and the critical nets are rerouted to remove overlaps. The non-critical nets are then unhidden. The non-critical nets and rerouted critical nets are then rerouted so as to remove overlaps.
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US Patent 07134112 Incremental routing in integrated circuit design US Patent 7134112 Incremental routing in integrated circuit design
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Patent Number
071341120
Patent Number
71341120
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Current Assignee
Patent Jurisdiction
Patent Number
071341120
Date of Patent
November 7, 2006
0Patent Application Number
106246150
Date Filed
July 21, 2003
0Official Website
Patent Primary Examiner
Edits on 8 Jun, 2022
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US Patent 07134112 Incremental routing in integrated circuit design
Infobox
Is a
Current assignee
Patent jurisdiction
Patent number
07134112
Date of patent
November 7, 2006
Patent application number
10624615
Date Filed
July 21, 2003
Patent primary examiner
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