US Patent 7135900 Phase locked loop with adaptive loop bandwidth

A semiconductor device that includes an adaptive phase locked loop with improved loop stability and a faster locking rate. In one embodiment, this is accomplished in a manner that does not require an additional second charge pump for loop stability, and therefore the resulting phase locked loop of the present invention consumes less chip die area. In another embodiment, multiple charge pumps are used and the resulting response time for locking is improved over that which can be achieved by conventional embodiments.