Patent attributes
A FIFO circuit includes a memory such as a register array having a plurality of storage locations. One or more data inputs can be coupled to the memory for receiving data that is to be stored therein. A control circuit controls the storage of data received from the one or more data inputs into the memory. In one embodiment, a particular one (e.g., memory location 0) of the plurality of storage locations is used as the location from which all data from the memory is outputted from. A multiplexer is used to move the data from within the memory into this particular memory location. The control circuit includes circuitry which allows for data received from the one or more data inputs to be stored substantially at the same time into the memory. In another embodiment, the FIFO circuit includes one data input for receiving data from a write bus and a second data input for receiving data from a read bus. A counter is used to store the pointer to the storage location within the memory were the write bus data is to be stored and a FIFO is used to store the pointer information to the storage location within the memory were read data bus data is to be stored that is received by the FIFO circuit.
