Patent attributes
To provide a level shift circuit which has reduced power consumption. A level shift circuit includes level shifters and a control unit. The control unit generates control signals for controlling operation states of the level shifters, respectively. The control unit has an R memory Mr1, a G memory Mg1, and a B memory Mb1. The G memory Mg1 has a stored content which is set to an operation permission state by means of a low-amplitude selection signal RSEL and which is reset to an operation inhibition state by means of a low-amplitude selection signal BSEL. During a period from the time when the low-amplitude selection signal BSEL becomes active up to the time when the low-amplitude selection signal RSEL becomes active, the operation of the level shifter stops. As a result, power consumption decreases.