US Patent 7136314 Memory device and test method thereof

A memory device and a test method thereof enable verification of failure of a cell region by intercepting bit lines connected to the cell region in a write-verify-read test. The memory device comprises a plurality of bit line switches and a separation control unit. The bit line switches connect the bit lines of the bit line sense amplifier to those of the selected cell array in response to a bit line separation control signal in a normal mode, separate the bit lines of the bit line sense amplifier from those of the unselected cell array, and separate the bit lines of the bit line sense amplifier from those of the cell array in response to the bit line separation control signal in a test mode. The separation control unit disables the bit line separation control signal in response to a test mode signal in the test mode.