US Patent 7138284 Method and apparatus for performing whole wafer burn-in

A method and apparatus for burning in a semiconductor wafer having a plurality of active devices utilizes temporary conductive interconnect layers to separately couple at least a portion of the anodes of the active devices together as well as at least a portion of the cathodes of the devices together. A simplified probed pad, having a reduced number of contacts may then be utilized to apply a substantially constant voltage or current to the devices. The temporary conductive interconnect layer may be patterned to include device level resistors or array level resistors that may be used to mitigate the effects of short circuits or open circuits on the processing of the devices.