US Patent 7138322 Semiconductor device and fabrication method therefor

An n-type channel diffused layer and an n-type well diffused layer are formed in the top portion of a semiconductor substrate, and a gate insulating film and a gate electrode are formed on the semiconductor substrate. Using the gate electrode as a mask, boron and arsenic are implanted to form p-type extension implanted layers and n-type pocket impurity implanted layers. Fluorine is then implanted using the gate electrode as a mask to form fluorine implanted layers. The resultant semiconductor substrate is subjected to rapid thermal annealing, forming p-type high-density extension diffused layers and n-type pocket diffused layers. Sidewalls and p-type high-density source/drain diffused layers are then formed.