US Patent 7139185 FeRAM having common main bit line

A nonvolatile ferroelectric memory device has an improved cell array structure where one main bit line is connected in common to a plurality of sub bit lines, thereby reducing the layout area of the memory and facilitating the process. The nonvolatile ferroelectric memory device having a common main bit line comprises a plurality of cell array blocks, a plurality of sense amplifiers, a main amplifier unit, and a data bus unit. The plurality of cell array blocks, which include main bit lines shared by a plurality of sub bit lines each adjacent left and right to the main bit line, induce a sensing voltage of the main bit line depending on a voltage applied to the plurality of sub bit lines by cell data.