US Patent 7142028 Clock duty ratio correction circuit

A clock duty ratio correction circuit corrects a duty ratio of internal clock signals at 1:1. The clock duty ratio correction circuit comprises a clock buffer unit, a charge pump unit, a comparison control unit, a voltage comparison unit, a counter and a D/A converter. The clock duty ratio correction circuit converts a differential internal clock signal into a voltage level corresponding to the pulse width of the differential internal clock signal, and compares the voltage level to generate a count signal. Additionally, the clock duty ratio correction circuit divides a reference voltage at a predetermined ratio in response to the count signal to generate a duty ratio correcting signal, and corrects the duty ratio of the differential internal clock signal by using the voltage level difference of the duty ratio correcting signal.