Patent attributes
One aspect of this disclosure relates to a memory cell. Various memory cell embodiments include an isolated semiconductor region separated from a bulk semiconductor region, an access transistor and a vertically-oriented thyristor formed in a trench extending between the isolated and bulk semiconductor regions. The access transistor includes a first diffusion region connected to a bit line, a second diffusion region to function as a storage node, a floating body region, and a gate separated from the floating body region by a transistor gate insulator. The isolated semiconductor region includes the first and second diffusion regions and the floating body region of the access transistor. The thyristor has a first end in contact with the bulk semiconductor region and a second end in contact with the storage node. The thyristor is insulated from the floating body region by a thyristor gate insulator. Other aspects and embodiments are provided herein.
