Is a
Patent attributes
Current Assignee
0
Patent Jurisdiction
Patent Number
Patent Inventor Names
Yi-Sheng Hsieh0
Wei-Min Lin0
Wei-Tsun Shiau0
Wen-Tai Chiang0
Chih-Wei Yang0
Date of Patent
December 5, 2006
0Patent Application Number
107101990
Date Filed
June 25, 2004
0Patent Primary Examiner
Patent abstract
A MOS transistor including a substrate, a gate dielectric layer on the substrate, a stacked gate on the gate dielectric layer, and a source/drain in the substrate beside the stacked gate is provided. In particular, the stacked gate includes, from bottom to top, a first barrier layer, an interlayer, a work-function-dominating layer, a second barrier layer and a poly-Si layer, wherein the work-function-dominating layer includes a metallic material.
Timeline
No Timeline data yet.
Further Resources
No Further Resources data yet.
