US Patent 7145356 Circuits for transistor testing

Disclosed is a circuit for transistor testing, by which electrical stresses of separate conditions can be simultaneously applied to a plurality of transistors, respectively. According to one example, such a circuit may include a plurality of contact pads connectable to a plurality of terminals of a plurality of transistors, a plurality of first resistors connected to a plurality of gates of a plurality of the transistors, respectively by voltage distribution according to a resistance ratio, respectively, and a plurality of second resistors connected between a plurality of gate electrodes and drains of a plurality of the transistors, respectively wherein a plurality of voltages applied to a plurality of the gates of a plurality of the transistors are dropped by a plurality of the second resistors to be applied to a plurality of drains of a plurality of the transistors, respectively.