Patent attributes
A data synchronization arrangement is provided that is fail-safe at high speed and low power consumption, for exchanging clocked data between different clock domains running in a digital processing equipment at the same clock frequency but at an arbitrary relative phase shift. A register arrangement has a predetermined number of parallel registers, each register having a data input, a write clock input, a read clock input and a data output. A write select multiplexer has an input receiving a write clock signal from a first clock domain, one clock output for each of the parallel registers and connected to a write clock input of a respective register, and one write select input for each clock output. A read select multiplexer has an input receiving a read clock signal from a second clock domain, one clock output for each of the parallel registers and connected to a read clock input of a respective register, and one read select input for each clock output. A write select shift register has a number of stages corresponding to the predetermined number of registers and an output stage looped back to an input stage.
