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US Patent 7146454 Hiding refresh in 1T-SRAM architecture

Patent 7146454 was granted and assigned to Cypress Semiconductor Corporation on December, 2006 by the United States Patent and Trademark Office.

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Date Filed
April 16, 2002
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Date of Patent
December 5, 2006
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Patent Application Number
10124773
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Patent Citations Received
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US Patent 12086410 Ferroelectric memory chiplet in a multi-dimensional packaging with I/O switch embedded in a substrate or interposer
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US Patent 11844223 Ferroelectric memory chiplet as unified memory in a multi-dimensional packaging
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US Patent 11841757 Method and apparatus for cycle-by-cycle clock gating of ferroelectric or paraelectric logic and CMOS based logic
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US Patent 12001266 Method and apparatus for managing power of ferroelectric or paraelectric logic and CMOS based logic
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US Patent 12019492 Method and apparatus for managing power in a multi-dimensional packaging
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US Patent 12026034 Method and apparatus for heuristic-based power gating of non-CMOS logic and CMOS based logic
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US Patent 11694940 3D stack of accelerator die and multi-core processor die
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US Patent 11764190 3D stacked compute and memory with copper pillars
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US Patent 11776598 Data processing circuit and device
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US Patent 11784164 3D stacked compute and memory with copper-to-copper hybrid bond
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Patent Inventor Names
Joseph Tzou
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Jun Li
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
7146454
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Patent Primary Examiner
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Pierre-Michel Bataille
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